FIG. 1 shows a plasma chamber which may, for example, be used in the fabrication of semiconductor integrated circuits. As shown, a wafer W (e.g., on which one or more semiconductor integrated circuits are formed) is positioned between first and second electrodes e1 and e2 located at opposite sides of the chamber. The wafer W is also located between north m1 and south m2 poles of a magnet also on opposite sides of the chamber, which sides are orthogonal to the sides at which the electrodes e1 and e2 are located. A low pressure gas G is introduced into the plasma chamber through an inlet port, such as a shower head S. A voltage source V applies an oscillating voltage (of, for example, 13.58 MHz) across the electrodes e1 and e2 to produce an electric field E directed between the two electrodes e1 and e2. This tends to cause the molecules of the low pressure gas G to gyrate in a cycloid motion. The north and south poles m1 and m2 of the magnet introduce a magnetic field B directed between the two poles, which magnetic field B is orthogonal to the electric field E. This tends to increase the collisions of the gyrating molecules thereby completely ionizing them to form the plasma P over the wafer W. A coolant C, such as liquid He, may be circulated on the underside of the wafer W to cool it during treatment.
FIG. 2 shows a more detailed view of certain parts of an actual plasma chamber 100, such as the MXP Centura.TM., distributed by Applied Materials, Inc..TM., located in Santa Clara, Calif. The chamber 100 has cylindrically shaped sidewalls 105. A cathode 110 is located at the bottom of the chamber 100. A pedestal 120 is secured to the cathode 110. (Actually, additional parts may be secured to the cathode 110 between the cathode 110 and the pedestal 120, such as an O-ring and aluminum sheet interface. These are omitted for sake of brevity.) The pedestal 120 is secured by screwing screws through the holes 122 of the pedestal 120 and the holes 112 of the cathode 110. A quartz pedestal liner ring, not shown, may then be placed in the chamber 100 surrounding the pedestal 120 (for purposes of improving the uniformity of the flow of the plasma gas over the entire wafer W). A transparent quartz cover or focus ring 150 may then be secured to the top of the chamber 100 to form a gas-tight seal, thereby confining the plasma P within the chamber 100 and isolating the wafer W from external contamination. As shown, the quartz cover or focus ring 150 is secured by screwing screws 130 through holes 132 to the chamber 100 or another part secured therein (not shown for sake of brevity). A quartz cap 140 may be placed on top of each screw 130.
The wafer W may be secured to the pedestal 120 in one of two ways. The pedestal 120 can be an electrostatic chucking pedestal. Such a pedestal 120 can generate an electrostatic charge that holds the wafer W in place during treatment. Alternatively, an ordinary pedestal 120 may be used. In such a case, the wafer W is then clamped to the pedestal 120 using a clamping ring 160. As shown, the clamping ring 160 has plural tips 170 which extend radially towards the interior of the ring 160. The dimensions of the clamping ring 160 are such that the ring 165 thereof has a greater diameter than the wafer W and does not touch the wafer. Rather, only the tips 170 contact and touch the wafer W. The tips 170 have holes 172 to enable screwing the clamping ring 160 to the pedestal 120 using (e.g., metal) screws 131 (which in turn are covered by graphite plugs, not shown) so that the tips 170 contact and press down on the wafer W, thereby holding it in place.
Plasma treatment is commonly used to etch structures on the wafer, such as polycrystalline silicon (poly) and oxide structures. Specifically, wafer structures not to be etched are typically covered with a mask whereas wafer structures to be etched are left exposed. The treatment using the plasma erodes the exposed structures.
Such a plasma erosive effect is also incurred by the various parts within the chamber 100. This reduces the life time of the parts. Moreover, because such parts are eroded while treating the wafer, the eroded material of the parts is introduced in the plasma chamber 100 as a contaminant. This tends to reduce the yield of the semiconductor integrated circuits formed from the treated wafers. Two parts specifically subject to the plasma erosive effect are the screws 130, used to secure the quartz focus ring or cover 150 (and, theoretically can be used to secure other objects within the plasma chamber 100), and the clamping rings 160.
FIGS. 3 and 4 show tips 171 and 173 of two conventional types of clamping rings 160. These rings 171 and 173 are preferably made of a polyimide material, such as the material marketed under the brand name Vespel.TM. by DuPont Engineering Polymers,.TM. located in Newark, Del. The tip 171 has two tapering planar sides s1 and s2 that meet at a planar surface s3 which is radially most distant from the ring 165. The surfaces s1 and s2 meet the surface s3 at sharp edges having negligible surface areas. The surface s3, itself, has a width 11 of only 1 mm. In addition, the top surface s4 also tapers so as to further reduce the height 14 of the surface s3 to about 1.5 mm. A recess having a length of about 13=3 mm in the radial direction is provided for receiving the wafer W thereunder when clamped. The tip 171 is most commonly used for poly etching applications.
The tip 173 also has tapering, planar surfaces s1' and s2'. These surface s1' meets one edge of cylindrical surface s5. The opposite edge of the cylindrical surface s5 meets an edge of the surface s3'. The opposite edge of the surface s3' meets an edge of the cylindrical surface s6, which is a mirror image of the surface s5. The opposite edge of the cylindrical surface s6 meets an edge of the surface s2'. Each cylindrical surface s5 and s6 constitutes less than .pi./2 of a rotation of the cylinder (due to the slight taper of the sides s1' and s2') and furthermore has a radius of less than 0.5 mm. As such, each of these surfaces s5 and s6 has a very small surface area and functions as a slightly blunted comer edge between the surface s3' and the surface s1' or s2', respectively. When viewed as such, the surface s3' separates the surfaces s1' and s2' by about 12.apprxeq.3 mm. The recess length 13' is also shorter. e.g., about 2 mm. The tips 173 are used for oxide etching applications.
The problem with the prior art rings 160 is that the tips 171 and 173 wear out very quickly by the above-noted plasma erosion phenomenon. The typical useful life of a ring 160 is about 230 hours, if the ring has tips 171, and 230 hours, if the ring has tips 173. The tips 171 and 173 are typically made longer (i.e., with a longer dimension 13 or 13') to increase their lifetime. However, this increases the tip contact area on the wafer thereby reducing the amount of surface area on the wafer that can be used for integrated circuits. In addition, the etching in the vicinity of the tips 171 or 173 is not as uniform as the remainder of the wafer. Moreover, due to the rapid erosion of the tips 171 and 173 of the rings 160, a large amount of contaminant particles are introduced during the plasma etching, thereby lowering yield.
It is an object of the present invention to overcome the disadvantages of the prior art.